1. Field of the Invention
The present invention relates generally to new semiconductor processes and integrated circuit structures which provide stacked via pillars in multilevel interconnection structures of semiconductor IC (integrated circuit) chips with high conductivity metallurgy such as copper and low-k dielectrics, to provide improved structural support and mechanical stability under large thermal excursions.
The present invention is particularly applicable to silicon microchip technologies where ruptures in metal interconnects due to thermal expansion can be mitigated by structural support provided by electrically non-functional stacked via pillars and fill patterns.
2. Description of the Prior Art
In order to meet the ever increasing demand for increased device density and performance, a semiconductor technology consisting of a low-k dielectric material and an interconnection wiring of copper metallurgy, defined by a dual damascene method, is the present day choice. Because, dry air has the theoretically lowest dielectric constant of one (1), most low-k materials such as aerogels, hydrogen silsesquioxane (HSQ), fluorinated organic polymers (e.g., SiLK, a trade mark of Dow chemical Co., Midland, Mich.), among others, have high porosity and, thereby, a negligibly small mechanical strength.
FIG. 1 is a schematic cross-section of a typical present day high performance interconnection structure. Such schemes generally have semiconductor devices (not shown) formed in silicon substrate 100 and locally interconnected by tungsten or polysilicon interconnection 101 which is imbedded in a passivation layer 103 of boro-phosphosilicate glass (BPSG) deposited just above the silicon substrate 100 to prevent any ionic migration into the device junctions. The high performance interconnection is formed with wirings of high conductivity metallurgies 131, 231, 331 on different levels, embedded in and insulated from each other with layers 112, 212, 312 of low-k dielectric ILD (inter level dielectric), and interconnected at desired points by metal filled via-studs 132, 232, 332. In order to prevent, or to reduce, the corrosive impurity ingression into interconnection wiring structure, as well as to impart mechanical stability, at least one layer of the top most layer of interconnection wiring 431 and via stud 432 is imbedded in one or more layers 412 of previous standard insulators such as silicon oxide, e.g., deposited by the plasma enhanced chemical vapor deposition (PECVD) using silane (SiH4) or tetraethylorthosilicate (TEOS) precursors. Accordingly, the present day high performance interconnection is comprised of one or more layers of high conductivity copper interconnections, imbedded in the low-k dielectric, and bounded on top and bottom by much denser layers of PECVD oxide and BPSG, respectively in the silicon substrate.
In such interconnection structures, a mechanical stress build up during thermal cycle stressing of chips has been observed. This stress build up has resulted in line buckling and liner deformation in stacked vias (LSM, SRAM) that lead to metal void formation and cracking within the interconnect. A reliability evaluation of such integrated circuit structures shown in FIG. 1 revealed excessive and premature failures due to circuit opens caused by the development of cracks in the wiring upon thermal cycling. FIG. 1 shows a typical crack formed in the stacked via-stud, in this example, at the interface of via-stud 332 and interconnection wiring 331, after 1000 thermal cycles between −65° C. and 150° C. Unlike the well known circuit open problem caused by electromigration, these cracks are not current flow dependent and may occur at any location beyond the interface of via-stud 332 and interconnection wiring 331. These cracks are generated upon thermal cycling alone; further, the propensity of crack generation is much greater in stacked via-studs, as shown in FIG. 1. Stacked via-studs are essential in high circuit density interconnections to feed power directly from the bus lines on the upper most wiring level to the local interconnects of semiconductor devices on lower most wiring levels. In an interconnection terminology, the stacked via-studs are comprised of alternatively stacked metal filled via studs 132, 232, and 332 and interconnect metal lines 131, 231, and 331. For the purposes of making stacked via-studs, the cross-sectional area of interconnection line segments 131, 231, 331 are made the same as the cross sectional areas of corresponding via-studs 132, 232, 332. One, or a set of redundant, stacked via-studs provide a direct connection from the top most level to the lower most levels of interconnection. The greater the ratio of stacked via-stud height (H) to diameter of the via-studs (D), the greater is the propensity for crack formation.
The continuing trend of dimensional shrinkage (smaller D) and increased wiring levels (larger H) in multilevel interconnections lead to much higher H to D ratios, thereby making the stacked via-studs of present and future interconnection wiring schemes increasingly more prone to cracks. It should be emphasized that the propensity of crack formation is much less in an interconnection scheme where the low k dielectric material is replaced by the previous standard dense dielectric material (e.g., PECVD oxide).
The crack propensity also increases with the range of temperature cycles and the number of cycles, showing that cracks are generated by metal fatigue, a phenomenon not been seen before in integrated circuit wiring. During thermal cycling of the chip, the stacked via-stud undergoes compressive/tensile stresses generated, respectively, by thermal expansion/contraction of the stacked via-stud due to mismatch in coefficients of thermal expansion between the metal and the surrounding dielectric. Because the stacked via-stud is mechanically pinned by the relatively much denser, and stiffer, layer of PECVD oxide at the top, and by the silicon substrate at the bottom, the difference in thermal expansion/contraction between the metal and the surrounding dielectric causes the stresses in the stacked via-stud. It should be noted that the thermal coefficient of expansion mismatch between copper and a typical low k dielectric material is several times higher than that between copper and PECVD oxide, thereby making the stacked via-stud of copper and low-k dielectric, e.g., SiLK, interconnection wiring scheme much more prone to crack formation than in stacked via-studs of present day multilevel interconnections comprised of a dense dielectric, e.g., PECVD oxide, at all levels of the interconnection. The crack formation in copper-SiLK interconnection wiring schemes is further aggravated due to nearly absent compressive stresses in SiLK dielectric material. Fatigue crack initiation is a surface phenomenon; it is well known that a surface coating improves the fatigue life. Dense oxide films, in deposited thin film form, have high intrinsic compressive stress, thereby exerting a lateral compressive force on via-studs. These compressive forces on the via-stud surface help delay, or prevent, the thermal fatigue failure in present day wiring schemes with a dense dielectric, e.g., PECVD oxide, material. The negligibly small compressive stress in low-k materials, along with the large thermal expansion mismatch between copper and low-k dielectric, e.g., SiLK, are root causes for the observed fatigue failure.
One of the major applications of stacked via-studs is to directly transfer large amounts of current from power buses on the top most level of interconnection wiring to power buses on lower levels in arrangements employing stacked via-studs formed between fat metal lines of power buses on different layers of interconnection wiring. In such cases, the propensity of fatigue crack formation is greatly increased in multilevel interconnection schemes with a low-k dielectric, e.g. SiLK, due to additional compressive stresses arising from the rigidity of fat metal lines acting on the stacked via-stud column.
U.S. Pat. No. 6,309,956 discloses designing chips by using dummy structures formed of an electrically conductive material which is mechanically stronger than the surrounding low-k dielectric material. The dummy structures remain electrically isolated from the conductive metal structures which comprise the electrical devices. The dummy structures are described to be rectangular in shape and positioned approximately parallel to the interconnects. The patent also discusses fabricating more than one level of dummy structures, in which these structures remain electrically and mechanically isolated from the dummy structures of a previous level.
A major distinction of the present invention is the use of stacked via structures extending vertically from the silicon dioxide substrate through all of the low-k dielectric layers to the top capping layer which function primarily to anchor the silicon dioxide substrate to the silicon dioxide capping layer. Another major difference of the present invention involves the placement and density of the stacked vias and fill structures. There is no description in this patent of the required distance between dummy structures, simply that they should be placed in the low-k dielectric layers approximately parallel to the interconnects. The present invention provides a stacked via density to maintain mechanical stability within the interconnects which is highly dependent on the amount of metal fill (including circuitry wiring) within the chip.
The copper areas of fill according to this patent are placed on one or more layers wherever large areas of dielectric exist. Significantly, the Cu fill areas are located in each layer after the wiring for that layer has been designed. In contrast to this patent, the stacked via pillars of the present invention are inserted into the chip design before the chip wiring is laid out and designed, and the wiring is designed around the stacked via pillars. Moreover, the stacked via pillars extend vertically from the substrate oxide all the way up to the top oxide cap.
The prior art has undoubtedly provided solutions and methods for relieving mechanical stress, however the solutions and methods have generally had an adverse impact upon design flexibility that restricts the techniques that circuit designers can use to design chips.